This invention relates to non-volatile memories, and more particularly to non-volatile memories having memory cells of floating gate type.
One previously proposed non-volatile memory is the erasable and programmable read only memory (EPROM) described in, for example, Japanese laid-open patent specification 3/34470.
FIG. 9 is a diagram of the above-mentioned non-volatile memory, which has connected therein a memory cell array 51, a row decoder 52, a column decoder 53, a column selection logic circuit 54, and a load circuit 55. FIG. 10 is a circuit diagram of the main parts of the memory cells, the load circuit 55 and the column selection logic circuit 54. FIG. 11 is a plan view of the memory cell array, and FIG. 12 is a perspective view of the memory cell corresponding to part of FIG. 11.
In this non-volatile memory, as shown in FIG. 12, aligned N type impurity-diffused layers 64 and 65 are formed on a silicon substrate 61 of, for example, P type, by ion implantation through the mask of a first polycrystalline silicon layer 63 which is formed on a first gate insulating film 62 on the substrate 61, and then a second gate insulating film 66 is formed over the substrate 61.
Thereafter, control gates 67 (which constitute the word lines) formed by strip-shaped second polycrystalline silicon layers are formed perpendicular to the impurity-diffused layers 64 and 65, and then the underlying second gate insulating film 66 and the first polycrystalline layer 63 are selectively etched away in a self-alignment manner through the mask of the control gates 67, so that floating gates formed by the first polycrystalline silicon layers 63 are built up on the substrate 61.
As shown in FIG. 11, the impurity-diffused layers 64 and 65 are alternately used as the bit lines and column lines, and channels are formed in the regions under the control gates 67 between the bit lines and the column lines, thus creating a large number of cells (M11, M12 . . . M33 . . .) for the achievement of a high-density integrated non-volatile memory.
The operation of the above non-volatile memory will now be described with reference to FIGS. 9 and 10.
When a word line Wn of, for example, the nth row is selected by an input row address to the row decoder 52, and when a column selection line Cn of, for example, the nth column is selected by an input column address to the column decoder 53, the word line Wn and the column selection line Cn are raised to a high level, and the other word lines and column selection lines of the other rows and columns stay at a low level.
At this time, transistors Q11, Q12 and Q13 connected to the column selection line Cn of the nth column are turned on, thus allowing a column line CLn to undergo discharge, and hence to be fixed to earth potential Vss. In addition, data paths are formed running from the odd and even bit lines, B1 and B2, to the odd and even data buses, DBL1 and DBL2, respectively. When the word line Wn of the nth row is selected, the memory cells (Q8 and Q9 as illustrated) connected to the word line Wn are selected.
At this time, if the memory cell Q8 is programmed to be logic "0", the memory cell Q8 remains in the off-state, and no signal is transmitted to the odd data bus DBL1. If the memory cell Q9 has no logic "0" written therein, or is programmed to be logic "1", the memory cell Q9 becomes in the on-state, and thus a current path is formed running from the even data bus DBL2 through the transistor Q13 to earth.
All the column lines and bit lines in the non-selected state are biased through transistors QS, Q6 and Q7 by a slightly higher voltage, Vcc, than the transition point of a sensing amplifier, not shown, connected to the odd and even data buses DBL1 and DBL2. This bias voltage prevents an unnecessarily large voltage change occurring when the bit lines which previously underwent discharge to drop to earth potential Vss are accessed.
Upon writing (programming), the word line Wn of the nth row and the column selection line Cn of the nth column are charged substantially to a program potential Vpp (&gt;Vcc). When the memory cell Q8 is not programmed, the odd data bus DBL1 is at the low level. When the logic "0" is programmed in the memory cell Q9, the even data bus DBL is raised to the program potential Vpp as described above.
This non-volatile memory has the following problems when the number of word lines is increased for high-density integration.
Firstly, the wiring resistance of the N type impurity-diffused layer for the bit lines or column lines is increased in proportion to the number of word lines. In other words, the memory cell current flowing in the memory cell is limited by the parasitic resistance inserted in series with the source and drain of the memory cell. Therefore, upon reading of data, the current flowing from the data bus to the memory cell decreases, so that the time during which the data bus is subjected to discharge becomes long. As a result, the access time is increased, so that it is difficult to read data at a high speed.
Secondly, since the bit lines and column lines constituting the memory cell array are made of the N type impurity-diffused layer, the junction capacitance between the impurity-diffused layer and the silicon substrate is added as a parasitic capacitance, thus increasing the time of discharge through the bit lines and column lines which precedes the discharge through the data bus.
Thirdly, since the memory cell current is limited by the series resistance of the source and drain of the memory cell, it is difficult to assure the current for writing data in the memory cell. The writing current usually needs to be about 1 mA. Since the writing voltage is specified generally as 12.5.+-.0.5V, it is absolutely necessary that the total resistance of the resistance of the bit line and column line and the working resistance of the memory cell be 12.5 k.OMEGA. or below.
The sheet resistance of an N type impurity-diffused layer is usually 10 to 50 .OMEGA./.quadrature.. In addition, referring to FIG. 12, if the first polycrystalline silicon layer (floating gate) 63 and the second polycrystalline silicon layer (control gate) 67 are designed on the same rule, the resistance value of the N type impurity-diffused layers 64 and 65 per row is at least 20 .OMEGA., and thus the number of rows (=the number of word lines) cannot be increased to 625 or above because the total resistance of the impurity-diffused layers becomes about 12.5 k.OMEGA..
This means that when the number of rows is selected to be equal to that of columns in accordance with the structure of the typical memory cell array 51, it is difficult to realize a larger-capacity non-volatile memory using the above high-density memory cells than 256 kbits.
Moreover, when the memory cells are integrated at a high density, the numbers of bit lines and column lines are increased with the increase of the number of memory cells, and thus it is also necessary to increase the number of the output terminals of the peripheral circuits such as the column decoder 53 and the load circuit 55. Since in this non-volatile memory the arrangement pitch of the output terminals of the peripheral circuits is the same as that of the bit lines and column lines in the memory cell array 51, the output terminals of the peripheral circuits must also be considered to be integrated at a high density in accordance with the increase of the integration density of the memory cells. Therefore, it is very difficult to design the non-volatile memory.